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freescale semiconductor data sheet: product preview document number: sc33690ds rev. 5, 02/2007 ? freescale semiconductor, inc., 2007. all rights reserved. this document contains information on a prod uct under development. freescale reserves the right to change or discontinue this product without notice. MC33690 soic-20 the standalone tag reader circ uit (starc) is an integrated circuit dedicated to the automo tive immobilizer applications. it combines the antenna drivers and demodulator necessary to interface with a transponder. a low dropout voltage regulator and a physical interface fully compatible with the iso 914 1 norm are also available. the starc is fabricated with the smartmostm3.5 technology. this process is a double layer metal 1.4m 45v technology, combining cmos and bipolar devices. ? contactless 125 khz tag reader module: ? self synchronous sample and hold demodulator ? amplitude or phase modulation detection ? high sensitivity ? fast read after write demodulator settling time ? low resistance and high curr ent antenna drivers, 2w @ 150ma (typ.) ? bidirectionnal data transmission ? multi-tag, multi-scheme operation ? low dropout voltage regulator: ? wide input supply voltage range from 5.5v up to 40v ? output current capability up to 150ma dc with an external power transistor ? 5v output voltage with a 5 % accuracy ? low voltage reset function ? low current consumption in standby mode: ? 300a (typ.) ? iso 9141 transmitter and receiver module: ? input voltage thresholds ratiometric to the supply voltage ? current limitation ? output slew rate control ? no external protection device required MC33690 standalone tag reader circuit source td1 vdd td2 xtal2 xtal1 am k rx tx 1 2 3 7 4 5 6 8 13 12 11 10 9 14 vss vsup gate 15 16 17 20 19 18 mode1 mode2 rd lvr dout agnd cext pin connections ordering information device operating junction temperature range package MC33690dw MC33690dwe t j = ? 40c to 125c tj = ? 40c to 125c soic 20 soic 20 (rohs)
MC33690 standalone tag r eader circuit, rev. 5 freescale semiconductor 2 table of contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.1 tag reader module. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2 read function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3 write function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 5 iso 9141 physical interface . . . . . . . . . . . . . . . . . . . . . . . . . . .8 6 communication modes description . . . . . . . . . . . . . . . . . . . . .9 7 standalone configuration with one-wi re bus . . . . . . . . . . . .10 7.1 timing definitions for a 8 mhz crystal . . . . . . . . . . . . .11 8 standalone configuration with two-wire bus. . . . . . . . . . . . .12 9 direct connection to a microcontroll er configuration . . . . . . .13 10 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 11 supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 12 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 13 low-voltage reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 14 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 15 tag reader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 16 iso 9141 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 17 digital i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 18 pin definition and function. . . . . . . . . . . . . . . . . . . . . . . . . . .19 19 application schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 list of figures figure 1. standalone tag reader circuit . . . . . . . . . . . . . . . . . . . 3 figure 2. tag reader block diagram . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. current flow when buffers are switched off . . . . . . . . 7 figure 4. voltage regulator block diagram . . . . . . . . . . . . . . . . . 8 figure 5. iso 9141 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. mode access description in one-wire bus configuration . . . . . . . . . . . . . . . . . . . . 11 figure 7. configuration a state diagram . . . . . . . . . . . . . . . . . . 11 figure 8. modes access description in two-wire bus configuration . . . . . . . . . . . . . . . . . . . . . 12 figure 9. configuration b state diagram . . . . . . . . . . . . . . . . . . 12 figure 10.configuration c state diagram . . . . . . . . . . . . . . . . . 13 figure 11.low voltage reset waveform . . . . . . . . . . . . . . . . . . 15 figure 12.demodulator parameters definition . . . . . . . . . . . . . . 17 figure 13.vsup, vdd, and source internal circuits . . . . . . . . . 19 figure 14.gate internal circuits . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 15.td1, td2, dout, and rx internal circuits . . . . . . . . 19 figure 16.agnd internal circuits. . . . . . . . . . . . . . . . . . . . . . . . 20 figure 17.cext internal circuits . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 18.rd internal circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 19.mode1, mode2, and tx inte rnal circuits . . . . . . . . 20 figure 20.lvr internal circuits . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 21.xtal2 and xtal1 internal circuits . . . . . . . . . . . . . . 21 figure 22.am internal circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 23.k internal circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 24.standalone configuration with one-wire bus . . . . . . 23 figure 25.standalone configuration with two-wires bus . . . . . 24 figure 26.direct connection to a microcontroller. . . . . . . . . . . . 25 list of tables table 1. maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 4 table 3. pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . 4 table 4. communication modes description. . . . . . . . . . . . . . . 10 table 5. supply current specifications . . . . . . . . . . . . . . . . . . . 14 table 6. voltage regulator specifications . . . . . . . . . . . . . . . . . 14 table 7. low-voltage reset specifications . . . . . . . . . . . . . . . . 15 table 8. oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . 15 table 9. tag reader specifications. . . . . . . . . . . . . . . . . . . . . . 16 table 10.iso 9141 interface specifications . . . . . . . . . . . . . . . . 17 table 11.digital i/o specifications . . . . . . . . . . . . . . . . . . . . . . . 18
MC33690 standalone tag r eader circuit, rev. 5 freescale semiconductor 3 figure 1. standalone tag reader circuit vdd vbat vsup gate source vdd vss td1 td2 rd xtal1 xtal2 mode1 mode2 dout lv r voltage regulator am cext agnd tag reader tx rx iso 9141 interface vbat r a c a l a r 1 r 2 c ext k 10mf 10nf 8mhz 510w c 1 optional: external n channel mos required for sourced current > 50ma. a recommended reference is mmft 3055vl from freescale.
MC33690 standalone tag r eader circuit, rev. 5 freescale semiconductor 4 table 1. maximum ratings rating symbol value unit supply voltage v sup v ss ? 0.3 to + 40 v supply voltage without using the voltage regulator (v sup =v dd ) v dd v ss ? 0.3 to + 7v voltage on source ? v ss ? 0.3 to + 40 v current into/from gate ? 0 ma voltage on gate ? v ss ? 0.3 v voltage on pins: mode1/2, cext, dout, lvr, xtal1/2, rx, tx ?v ss ? 0.3 to v dd + 0.3 v voltage on rd ? 10 v voltage on k and am ? v ss ? 3 to 40 v current on td1 and td2 (drivers on and off) ? 300 ma voltage on agnd ? v ss 0.3 v esd voltage capability 1 ? 2000 v esd voltage capability 1 ? 200 v solder heat resistance test (10s) ? 260 c junction temperature t j 170 c storage temperature t s ? 65 to + 150 c 1 human body model, aec-q100-002 rev. c; machine model, aec-q100-003 rev. e. table 2. thermal characteristics characteristic symbol value unit junction to ambient thermal resistance (soic20) r th 80 c/w table 3. pin function descriptions pin function description 1 vsup power supply 2 source external n channel transistor source 3 gate external n channel transistor gate 4 td1 antenna driver 1 output 5 vss power and digital ground 6 vdd voltage regulator output 7 td2 antenna driver 2 output 8 mode1 mode selection input 1 9 mode2 mode selection input 2 10 rd demodulator input
description MC33690 standalone tag r eader circuit, rev. 5 freescale semiconductor 5 1 description 1.1 tag reader module the tag reader module is dedicated for automotive or industrial applications where information has to be transmitted contactless.the tag reader module is a write/read (challenge/response) controller for applications that a demand high security level. the tag reader module is connected to a serial-tuned lc circuit that generates a magnetic field power supplying the tag. the use of a synchronous sample and hold technique allows commun ication with all available tags using admittance switching producing absorption of the rf field. load amplitude or phase shift m odulation can be detected at high bit rates up to 8 khz. the typical operational carrier frequenc y of the tag reader module with an 8 mhz clock is 125 khz. 11 agnd demodulator ground 12 cext comparator reference input 13 dout demodulator output (5v) 14 lvr low voltage reset input/output 15 xtal2 oscillator output 16 xtal1 oscillator input 17 am amplitude modulation input 18 k iso 9141 transmitter output and receiver input 19 rx iso 9141 receiver monitor output 20 tx iso 9141 transmitter input table 3. pin function descriptions (continued)
MC33690 standalone tag r eader circuit, rev. 5 read function freescale semiconductor 6 figure 2. tag reader block diagram 2 read function when answering to the base sta tion, a transponder generates an absorption modula tion of the magnetic field. it results in an amplitude/phase modulation of the current across the antenna. this information is picked up at the antenna tap point between the coil and the capacitor. an external resistive ladder down scales this voltage to a level compatible with the demodulator in put voltage range (see section 15, ?tag reader? ). the demodulator (see figure 2 ) consists of: ? an input stage (emitter follower) ? a sample and hold circuit ? a voltage follower ? a low offset voltage comparator the sampling time is automatically set to ta ke into account a phase shift due to the to lerances of the ante nna components (l an d c) and of the oscillator. the allowed phase shift measured at the input rd ranges from ? 45 to + 45 . assuming that the phase d c q + - 1/32 counter 1/2 rd cext agnd buffer vdd 500ns s/h buffer comparator 100kw 8mhz clock 8 mhz data out interface 125 khz td2 11.25 , 22.5 , 33.75 , 45 , 56.25 , 67.5 , 78.75 , 90 am data + - 4mhz 125 khz lv r shutdown td1 10nf +0 , -11.25 , -22.5 , -33.75 , -45 , -56.25 , -67.5 , -78.75 c a l a r 1 r 2 c ext r a vdd + - setup and preload self synchronous sample and hold 500ma
write function MC33690 standalone tag r eader circuit, rev. 5 freescale semiconductor 7 reference is the falling edge of the driving signal td1, this leads to a sampling time phase ranging from ? 78.75 to 90 with discrete steps of 11.25 . after reset condition, the sampling time phase is + 11.25 . the antenna phase shift evaluation is only do ne after each wake-up command or after rese t. this is necessary to obtain the best demodulator performances. to ensure a fast demodulator settling time after wake-up, reset, or a write sequence, the external capacitor cext is preloaded at its working voltage. this preset occurs 256s after switchin g the antenna drivers on and its duration is 128s. after wake-u p or reset, the preset has the same duration, but begins 518s after clock settling. after power on reset, vsup must meet the minimum specified value, en abling the nominal op eration of vdd, before the start of the preset. otherwise, the preset must be done through a standby/wake-up sequence. 3 write function whatever the selected configuration (see section 6, ?communication modes description? ), the write function is achieved by switching on/off the output drivers td1/2. after the drivers have been set in high impedance, th e load current flows alternativ ely through the internal diodes to vss and to vdd (see figure 3 ). figure 3. current flow when buffers are switched off 4 voltage regulator the low dropout voltage regulator provides a regulated 5v supply for the internal circuitry. it can also supply external peripherals or sensors. the input supply voltage ranges from 5.5v to over 40v. this voltage regulator uses a series combination of high voltage ldmos and low voltage pmos transistors to provide regulation. an external low esr capacitor is required for the regulator stability. the maximum average curren t is limited by the power dissipation capability of the so 20 package. this limitation can be overcome by connecting an external n channe l mos parallel with the internal ldmos. the threshold voltage of this transistor must be lower than the one of the internal ldmos (1.95v typ.) to prevent the current from flowing into the ldmos. its breakdown voltage must be higher than the maximum supply voltage. a low-voltage reset function monitors the vdd output. an inte rnal 10a pull-up current source allows, when an external capacitor is connected between lvr and gnd, to generate delays at power up (5ms typ. with c reset = 22nf). the lvr pin is c a l a r 1 r a td1 vdd td2 vdd i load
MC33690 standalone tag r eader circuit, rev. 5 iso 9141 physical interface freescale semiconductor 8 also the input generating the internal reset signal. applying a lo gic low level on this pin resets the circuit, all the interna l flip flops are reset, and drivers td1/2 are switched on. figure 4. voltage regulator block diagram 5 iso 9141 physical interface this interface module is fully compatible with the iso 9141 no rm describing the diagnosis line. it includes one transmitter (pin k) and two receivers (pins k and am). the input stages consist of high-voltage cm os triggers. the thresholds are ratiometri c to vsup. a ground referenced current source (2.5a typ.) pulls down the input when unconnected. when a negative voltage is applied on the k or am li nes, the input current is internally limited by a 2k resistor (typ.) in series with a diode. a current limitation allows the transmitter to drive any capacitiv e load and protects against shor t circuit to the battery volt age. an overtemperature protection sh uts the driver down when the junction temp erature exceeds 150c (typ ). after shutdown by the overtemperature protection, the driver can be switched on again if the junction temperature has decreased below the threshold and by applying an off/on command, coming from the de modulator in configurations a a nd b, or directly applied on the input tx in configuration c (see table 4 ). the electromagnetic emission is reduced because of the voltage slew rate control (5v/s typ.). 1 mhz oscillator charge pump voltage reference and biasing generator + - vsup gate source vdd comparator n channel ldmos p channel mos + - lv r vbat c 1 vdd 10mf 100nf c 3 c 2 10ma vdd c reset vdd reset
communication mo des description MC33690 standalone tag r eader circuit, rev. 5 freescale semiconductor 9 figure 5. iso 9141 interface 6 communication modes description the starc offers three different communicat ion modes. therefore, it can be used as a standalone circuit connected to an electronic control unit (ecu) through a bus line or it can be dir ectly connected to a microcontroller in case of a single board architecture. command rx k tx k line vbat 2kw over temperature current limitation detector vdd vdd tag reader module output am vsup from configuration controller am data from configuration controller l line vsup vdd gnd 2.5ma gnd 2.5ma 2kw gnd gnd
MC33690 standalone tag r eader circuit, rev. 5 standalone configuration with one-wire bus freescale semiconductor 10 7 standalone configuration with one-wire bus when a low level is applied on pins mode1 and mode2, the circuit is in configuration a (see figure 24 ). after power on, the circuit is set into read mo de. the demodulator output is directly routed to the iso 9141 interface output k. the circuit can be set into write mode at anytime by violation of all possible patterns on the single wire bus during more than 1ms. then, the k line achieves the amplitude modulation by switching on/off both antenna drivers. after 1ms of inactivity at the end of the ch allenge phase (bus in idle recessive one state), the circ uit is set back into read mode. the circuit can be put into standby mode by forcing the k line at zero during more than 2 ms after entering the write mode. after the k line is released, the circuit sends an acknowledge pulse before entering into standby mode. in standby mode, the oscillator and most of the internal biasi ng currents are switched off. therefore, th e functions (tag reader, iso 9141 driver) a re inactive except the voltage regulator and th e iso 9141 receiver on pin k. the driver output td1 forces a low level and td2 forces a high level. a rising edge on k wakes up the circu it. after completion of the wake-up sequence, the circuit is automatically set in read mode. in configuration a, dout and rx outputs alwa ys force a low level and tx is disabled. table 4. communication modes description configuration configuration pins pin status function description type bus type name mode1 mode2 standalone 1 wire (vbat) a 0 0 k output/input: ? demodulator output ? amplitude modulation input ? shutdown/wake-up am must be connected to vsup dout forces a low level 2 wires (vbat) b 0 1 k output: ? demodulator output am input: ? amplitude modulation input ? shutdown/wake-up dout forces a low level direct connection to a mcu 2 wires (vdd) c 1 x dout output: ? demodulator output am input: ? amplitude modulation input mode2 input: ? shutdown/wake-up 1 k output/input (standalone iso 9141 interface): ? driven by tx and monitored by rx 0 k input (standalone iso 9141 interface): ? monitored by rx ? tx disabled
standalone configuration with one-wire bus MC33690 standalone tag r eader circuit, rev. 5 freescale semiconductor 11 figure 6. mode access description in one-wire bus configuration figure 7. configuration a state diagram 7.1 timing definitions for a 8 mhz crystal the timing definitions for a 8 mhz crystal are: ?t ref is crystal oscillator period (125 ns typ.) ?t 0 =8064.t ref = 1.008ms typ. ?t 0 ?=7932.t ref = 0.992ms typ. ?t 1 =16256.t ref = 2.032ms typ. ?t 1 ?=16128.t ref = 2.016ms typ. ?t 2 =4096.t ref , = 512s typ. t 0 is the minimum time required to guarantee the device toggles fr om read to write (or from write to read). however, the starc may toggle from read to write (or from write to read) between t 0 and t 0 ?. t 1 is the minimum time required to guaran tee the device toggles from write to standby. however, the starc may toggle in standby between t 1 and t 1 ?. k line t 0 t < t 0 ?+t 1 ? 1 0 0 0 1 1 read mode write mode k line t ?t 0 read mode write mode k line t ? t 1 standby mode write mode read to write mode: write to read mode: write to standby mode: standby mode to read mode: standby mode read mode wake-up sequence k line acknowledge t 2 t 2 read write td1/2 write td1/2 off standby t 0 k line low k line high < t 0 ? t 1 k line low t 0 k line high wake-up k line low reset k switching
MC33690 standalone tag r eader circuit, rev. 5 standalone configuration with two-wire bus freescale semiconductor 12 8 standalone configuration with two-wire bus when a low level is applied on mode1 and a high level on mode2, the circuit is in configuration b (see figure 25 ). the k pin is set as an output sending the demodulated data. the am pin is set as a vsup referenced input pin receivi ng the amplitude modulation and the shutdown/wake-up commands. forcing high and low levels on am achieves the amplitude modulation by switching on/off both antenna drivers. this amplitude modulation can be monitored on the k output and allows antenna short and open circuit diagnosis. the circuit can be put into standby mode by forcing the am line at zer o during more than 2 ms. the circuit sends an acknowledge pulse before entering into standby mode. in standby mode, the oscillator and most of the internal biasin g currents are switched off. theref ore, the functions (tag reade r and iso 9141 driver) are inactive except for the voltage regu lator and the iso 9141 receiver on pin am. the driver output td1 forces a low level and td2 a high level. a rising edge on am wakes up the circuit. after completion of the wake-up sequence, the circuit is automatically set in read mode. in configuration b, dout and rx outputs alwa ys force a low level and tx is disabled. figure 8. modes access description in two-wire bus configuration figure 9. configuration b state diagram am line 1 0 0 0 1 1 data read drivers off am line t ? t1 standby mode read and write sequences: 1 0 0 0 1 1 k line entering into standby mode: k line data write modulation data write am line monitoring drivers on wake-up sequence data read t2 t2 t1 coming out of standby mode: am line k line standby mode acknowledge td1/2 off td1/2 standby am line high wake-up am line low t1 am line low reset am line high am line low am switching
direct connection to a microcontroller configuration MC33690 standalone tag r eader circuit, rev. 5 freescale semiconductor 13 9 direct connection to a microcontroller configuration when a high level is applied on mode1, the circuit is in configuration c (see figure 26 ). the demodulated data are sent through dout. the am pin is set as a vdd referenced input pin receiving the am co mmand. forcing high and low levels on am achieves the amplitude modulation by switching on/off both antenna drivers. meanwhile, this amplitude modulation can be monitored on dout. this allows antenna shor t and open circuit diagnosis. the circuit can be put into standby mode by applying a low level on the mode2 pin. in standby mode, the oscillator and most of the internal biasing currents are switch ed off. therefore, the functions (tag r eader and iso 9141 interface) are inactive ex cept for the voltage regulator. the driver outputs td1 and td2 are fr ozen in their state (high or low level) before entering into standby mode. dout forces a low level. the iso 9141 interface k is stan dalone and can be directly c ontrolled by the input pin tx and monito red by the output rx. applying a logic high level on tx switches the output driver k on (dominant zero state when an external pull-up resistor is connected between k and vbat ). applying a logic low level turns th e driver off (one recessive state). rx monitors the voltage at the k pin. when the voltage is below the low threshol d voltage, rx forces a logic low level. when the voltage is above the high threshold voltage, rx forces a logic high level. in standby mode, tx is disabled and rx output monitors the voltage at the k pin. figure 10. configuration c state diagram 10 electrical characteristics typical values reflect av erage measurements at v sup = 12v and t j = 25 c. 11 supply current typical values reflect aver age measurements at 6v v sup 16v, v ss = 0v, t j = ?40 c to + 125 c, unless otherwise noted. td1/2 off standby wake-up mode2 low mode2 high mode2 low td1/2 am high am high am low reset am low switching
MC33690 standalone tag r eader circuit, rev. 5 voltag e regulator freescale semiconductor 14 12 voltage regulator typical values reflect aver age measurements at 6v v sup 16v, v ss = 0v, t j = ?40 c to +125 c, unless otherwise noted 13 low-voltage reset typical values reflect aver age measurements at 6v v sup 16v, v ss = 0v, t j = ?40 c to +125 c, unless otherwise noted table 5. supply current specifications parameter symbol test conditions and comments min typ max unit type pin vsup 9.1 standby mode current i sup1 ? ? 300 500 a? 9.2 operating mode current i sup2 circuit in configuration c no current sunk from vdd drivers td1/2 switched off tx forced to low ?1.52.5ma? table 6. voltage regulator specifications parameter symbol test conditions and comments min typ max unit type pins vsup and vdd 1.1 output voltage (5.5v v sup 40v) v vdd1 without external mos transistor, i out 50ma 4.75 5.0 5.25 v ? 1.3 total output current i vdd1 ??50ma? 1.5 load regulation v loadreg1 without external mos transistor, 1 to 50ma i out change ?2060mv? 1.9 output voltage (5.5v v sup 40v) v vdd2 with external mos transistor, i out 150ma the stability is ensured with a decoupling capacitor between vdd and vss: c out 10 f with esr 3 . the current capability can be increased up to 150ma by using an external n channel mos transistor (see figure 1 ). the main characteristics for choosing this component are vt < 1.8v and bvdss > 40v 4.7 5.0 5.3 v ? 1.11 total output current i vdd2 ? ? 150 ma ? 1.6 load regulation v loadreg2 with external mos transistor,1 to 150ma i out change ? 65 150 mv ? 1.4 line regulation (6v v sup 16v) v linereg i out = 1ma ???mv?
oscillator MC33690 standalone tag r eader circuit, rev. 5 freescale semiconductor 15 figure 11. low voltage reset waveform 14 oscillator typical values reflect aver age measurements at 6v v sup 16v, v ss = 0v, t j = ?40 c to + 125 c, unless otherwise noted table 7. low-voltage reset specifications parameter symbol test conditions and comments min typ max unit type pin lvr 1.6 low voltage reset low threshold v lv ro n because the voltage regulator and the low-voltage reset are using the same internal voltage reference, the low-voltage reset occurs only when the voltage regulator is out of regulation. see figure 11 4.1 4.35 4.6 v ? 1.7 low voltage reset hysteresis v lv r h 50 100 150 mv ? 1.12 pull-up current i lv ru p v lvr = 2.5v 5 10 15 a? 1.13 output resistance in reset condition r lv r v lvr = 2.5v 200 370 500 ? 1.14 input low voltage v illvr ? 0 ? 0.3 x v dd v? 1.15 input high voltage v ihlvr ? 0.7 x v dd ?v dd v? table 8. oscillator specifications characteristic symbol test condition and comments min typ max unit type pins xtal1, xtal2 8.0 input capacitance c xtal1 v xtal1 = 2.5v ? 5 ? pf ? 8.1 voltage gain v xtal2 / v xtal1 a osc v xtal1 = 2.5v ? 25 ? ? ? 8.3 clock input level v xtal1 this level ensures the circuit operation with an 8 mhz clock. it is applied through a capacitive coupling. a 1m resistor connected between xtal1 and xtal2 biases the oscillator input. 1.5 ? v dd vpp ? vdd lv r v lvron v lvron + v lvrh
MC33690 standalone tag r eader circuit, rev. 5 tag reader freescale semiconductor 16 15 tag reader typical values reflect aver age measurements at 6v v sup 16v, v ss = 0v, t j = ?40 c to + 125 c, unless otherwise noted table 9. tag reader specifications parameter symbol test conditions and comments min typ max unit type demodulator (pin rd) 2.0 input voltage range v inrd ? 345v? 2.2 input modulation frequency f mod ?0.548khz? 2.3 demodulator sensitivity v sense1 6.5v v sup 16v sensitivity is measured in the following application conditions: i antenna =50ma peak, v rd = 4v peak, c ext = 10nf, and square wave modulation f mod =f td1 /32. see figure 12 ?515mv? 2.31 demodulator sensitivity v sense2 6v v sup < 6.5v the sensitivity is measured in the following application conditions: i antenna = 50ma peak, v rd = 4v peak, c ext = 10nf, and square wave modulation f mod = f td1 /32 see figure 12 ?730mv? 2.4 demodulation delay t demod configuration c not including the delay due to the slew rate of the k output for configurations a and b see figure 12 ?7.510 s? 2.5 after write pulse settling time t settling1 ? ? 394 400 s? 2.6 recovery time after wake-up or reset from clock stable to demodulator valid output t settling2 clock stable condition implies v xtal1 meets the specification (see page 15). ? 646 700 s? drivers (pins td1, td2) 3.5 output carrier frequency to crystal frequency ratio r ftd/fxt al ??64??? 3.0 turn on/off delay t on/off ? ? ? 250 ns ? 3.1 driver1/2 low side out. resistance r tdl i load = 150ma dc ? 2.4 4 ? 3.2 driver1/2 high side out. resistance r tdh i load = -150ma dc ? 2.1 4 ?
iso 9141 interface MC33690 standalone tag r eader circuit, rev. 5 freescale semiconductor 17 figure 12. demodulator parameters definition 16 iso 9141 interface typical values reflect aver age measurements at 6v v sup 16v, v ss = 0v, t j = ?40 c to + 125 c, unless otherwise noted table 10. iso 9141 interface specifications parameter symbol test conditions and comments min typ max unit type receiver (pins k and am) 4.0 input low voltage v il ? ? ? 0.3 x v sup v? 4.1 input high voltage v ih ?0.65 x v sup ?40v? 4.2 input hysteresis voltage v hy1 ? 0.4 0.65 1.3 v ? 4.3 biasing current i b 0v v in 16v 135 a? 4.31 input current i bm -3 v in < 0 ? 2 ? 1?ma? 4.4 k to rx delay tdkrx ? 2 10 s? driver (pin k) 5.0 output falling edge slew rate sr f r pull-up = 510 , calculated from 20 % to 80 % of the output swing. 3.5 5 6.5 v/ s? 5.1 output rising edge slew rate sr r 3.5 5 6.5 v/ s? 5.2 rise fall slew rates symmetry sr symet ry ? 10 1v/ s? 5.3 output low voltage v olk i load = 25ma ? 1.1 1.4 v ? 5.4 input current (driver switched on or off) i ik ? 3v v in 0v ? 2? 0ma? 5.5 current limitation threshold i l 0v v in 40v 35 50 65 ma ? 5.6 thermal shutdown threshold th sdwn ? 130 150 170 c? demodulator v rd v sense t demod output (k or dout)
MC33690 standalone tag r eader circuit, rev. 5 digital i/o freescale semiconductor 18 17 digital i/o typical values reflect aver age measurements at 6v v sup 16v, v ss = 0v, t j = ?40 c to + 125 c, unless otherwise noted table 11. digital i/o specifications characteristic symbol test condition and comments min typ max unit type input (pins mode1, mode2, am, tx) 6.0 input low voltage v ild ? 0 ? 0.3 x v dd v? 6.1 input high voltage v ihd ? 0.7 x v dd ?v dd v? 6.2 input hysteresis voltage v hd ?.24.71v? output (pins dout,rx) 7.0 output low voltage v ol i load = 500ua 0 0.5 0.2 x v dd v? 7.1 output high voltage v oh i load = -500ua 0.8 x v dd 4.6 v dd v? 7.2 fall/rise time t f/r c load =10pf, calculated from 10 % to 90 % of the output swing ? ? 150 ns ?
pin definition and function MC33690 standalone tag r eader circuit, rev. 5 freescale semiconductor 19 18 pin definition and function the internal circuits co nnected to the pins of the device are shown in fi gures 13 ? 23, including the diodes used for esd protection. figure 13. vsup, vdd, and source internal circuits figure 14. gate internal circuits figure 15. td1, td2, dout, and rx internal circuits 16v vdd 6v 1 vsup 16v 2 source 40v 6 vdd gate 2k 30k 16v 9v idem 4 7 13 19 16v vdd td1 td2 dout rx
MC33690 standalone tag r eader circuit, rev. 5 pin definition and function freescale semiconductor 20 figure 16. agnd internal circuits figure 17. cext internal circuits figure 18. rd internal circuits figure 19. mode1, mode2, and tx internal circuits 8 agnd vss 500a 9 cext 16v 10v 10v 16v 10 rd 2k 16v 200a vdd tx idem 12 mode1 vdd 13 mode2 16v 11v 20 2k
pin definition and function MC33690 standalone tag r eader circuit, rev. 5 freescale semiconductor 21 figure 20. lvr internal circuits figure 21. xtal2 and xtal1 internal circuits 11v 2k vdd 16v 200 10a vdd 14 lvr vdd 16 xtal1 15 xtal2 11v 16v 2k 200
MC33690 standalone tag r eader circuit, rev. 5 pin definition and function freescale semiconductor 22 figure 22. am internal circuits figure 23. k internal circuits 16v vdd 40v vsup 2k 40v 22v 17 am 2a 22v vsup 22v 1k 2k 2a 40v 18 k vsup 22v 40v 16v
application schemes MC33690 standalone tag r eader circuit, rev. 5 freescale semiconductor 23 19 application schemes figure 24. standalone configuration with one-wire bus vbat vsup gate source td1 td2 rd xtal1 xtal2 mode1 mode2 dout lv r am cext agnd starc tx rx c ext 10mf 10nf 8mhz vdd vss 100nf nc nc vsup nc 510w vbat k vss c 1 c 3 c 2 r a c a l a r 1 r 2 note: if no external mos transistor is necessary to increase th e voltage regulator current capability, the pins gate and source must be left unconnected. in this configuration, the outputs rx and dout forc e a low level. c1 is not required for the starc functionality and only acts as a reserv oir of energy. to preserve the demodulator sensitivity, cext and r2 should be connected to agnd and vss connected to agnd using a low resistance path. nc nc 1mw 8.2pf 8.2pf
MC33690 standalone tag r eader circuit, rev. 5 application schemes freescale semiconductor 24 figure 25. standalone configuration with two-wires bus vbat vsup gate source td1 td2 rd xtal1 xtal2 mode1 mode2 dout lv r am cext agnd starc tx rx r a c a l a r 1 r 2 c ext 10mf 10nf vdd vss 100nf nc nc nc 510w vdd k vss c 1 c 3 c 2 vbat nc nc note: if no external mos transistor is necessary to increase t he voltage regulator current capability, the pins gate and source must be left unconnected. c 1 is not required for the starc functionality and only acts as a reservoir of energy. to preserve the demodulator sensitivity, c ext and r 2 should be connected to agnd and vss connected to agnd using a low resistance path. 8mhz 1mw 8.2pf 8.2pf
application schemes MC33690 standalone tag r eader circuit, rev. 5 freescale semiconductor 25 figure 26. direct connection to a microcontroller vbat vsup gate source td1 td2 rd xtal1 xtal2 mode1 mode2 dout lv r am cext agnd starc tx rx c ext 10uf 10nf vdd vss 100nf nc nc 510w vbat k vss c 1 c 3 c 2 vdd to microcontroller port to microcontroller port to microcontroller to microcontroller power supply pin r a c a l a r 1 r 2 note: if no external mos transistor is necessary to increase t he voltage regulator current capability, the pins gate and source must be left unconnected. c 1 is not required for the starc functionality and only acts as a reservoir of energy. to preserve the demodulator sensitivity, c ext and r 2 should be connected to agnd and vss connected to agnd using a low resistance path. 8mhz 1mw 8.2pf 8.2pf port/reset pin
document number: sc33690ds rev. 5 02/2007 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org ? freescale semiconductor, inc. 2007. all rights reserved.

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